Did MetaRAM Play a Role in Google’s Infrastructure Update to Caffeine>
In August, Google announced an upgrade to Google’s infrastructure named Caffeine, aimed at making the search engine faster. One of the developers behind the upgrade described it as an upgrade to the Google File System.
At the US Patent Office assignment database this morning, I noticed patents and patent applications assigned to Google on November 18, 2009, originally granted to startup MetaRAM.
If a search engine wanted to upgrade its capabilities, it might also upgrade the hardware that it uses. MetaRAM’s patents could potentially transform Google’s computing capacity dramatically.
I have no idea if Google’s Caffeine upgrade also includes a memory upgrade from MetaRAM at this point, but I suspect that the MetaRAM patent assignments could be related. Ownership of MetaRAM’s chip patents make that more likely.
The Wall Street Journal’s blog told us about the demise of MetaRAM, a startup with some very high profile founders, board members, and executives, including a CEO who was chief technology officer of Advanced Micro Devices Inc for ten years, and a Board of Directors member who was a former chief scientist of Sun Microsystems Inc. – Turning Out The Lights: Semiconductor Company MetaRAM
An interview with the original and former CEO of MetaRAM from May of 2008, provides a lot of insight into the direction that MetaRAM was taking – Pioneering Change in the Memory Market: MetaRam Visionary Fred Weber.
Did Google acquire MetaRAM or just the patent filings from the company? The WSJ blog post tells us that the company shut down without providing a date for its closing. However, LinkedIn profiles for people from MetaRAM still list their positions with the company as their present place of employment.
I haven’t been able to locate much in the way of recent news about MetaRAM, nor much that associates them with Google.
Will Google keep this new technology from MetaRAM in-house, and use it to reduce the costs of servers and workstations by a significant amount while increasing the amount of memory available to those systems? Or will they license or sell the technology directly, or both? So little is known at this point. There hasn’t been an announcement from Google or anyone from MetaRAM yet that I could find. I haven’t seen any rumors of the transaction behind the assignment of the patent filings anywhere on the Web either.
I’ve listed the granted patents and the patent applications from MetaRAM below. There are 49 of them in total; a number of them were filed more than once for one reason or another.
Granted Patents from Metaram:
Integrated memory core and memory interface circuit (7,515,453)
Abstract
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
Abstract
A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.
Interface circuit system and method for performing power saving operations during a command-related latency (7,581,127)
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
Methods and apparatus of stacking DRAMs (7,379,316) Methods and apparatus of stacking DRAMs (7,599,205)
Abstract
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
Power saving system and method for use with a plurality of memory circuits (7,580,312)
Abstract
A power-saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to identifying the at least one memory circuit, a power-saving operation is initiated in association with the at least one memory circuit.
System and method for simulating an aspect of a memory circuit (7,609,567)
Abstract
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Per various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
System and method for power management in memory systems (7,590,796)
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.
Pending Patent Applications from MetaRAM
Some of the patent applications below, originally assigned to MetaRAM. share names with granted patents above, and may contain the same or very similar content. There are also some pending patent applications with the same name and abstracts, and those have been grouped together below.
Apparatus and Method for Power Management of Memory Circuits by a System or Component Thereof (20080082763)
Abstract
An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g., power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
Combined Signal Delay and Power Saving System and Method for Use with a Plurality of Memory Circuits (20080123459)
Abstract
A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed
Emulation of Abstracted DIMMs using Abstracted DRAMs (20090216939)
Abstract
One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface.
The characteristics can be presented on the memory system interface via logic signals or protocol exchanges. The characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, many pipeline stages, many banks, a mapping to physical banks, several ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, many planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device.
One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.
Abstract
A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits
Abstract
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
Memory Circuit Simulation System and Method with Power Saving Capabilities (20080027697)
Abstract
A system and method are provided, including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power-saving operation.
Memory Circuit Simulation System and Method with Refresh Capabilities (20080027703)
Abstract
A system and method are provided, including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control the refreshing of the plurality of memory circuits.
Memory Circuit System and Method (20090024789) Memory Circuit System and Method (20090024790)
Abstract
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g., power management, simulation/emulation, etc.).
Memory Device with Emulated Characteristics (20080056014) Memory Device with Emulated Characteristics (20080126687) Memory Device with Emulated Characteristics (20080103753) Memory Device with Emulated Characteristics (20080126692) Memory Device with Emulated Characteristics (20080126689) Memory Device with Emulated Characteristics (20080109206) Memory Device with Emulated Characteristics (20080126688) Memory Device with Emulated Characteristics (20080104314)
Abstract
A memory subsystem is provided, including an interface circuit adapted for communication with a system and a majority of address or control signals of the first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
Memory module with memory stack and interface with enhanced capabilities (20070195613) Memory module with memory stack (20080126690)
Abstract
A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system to operate the memory stack as a single DRAM integrated circuit.
In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner.
In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.
In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details outlined in the abstract to constitute limitations to claims not explicitly reciting those details.
Memory Refresh System and Method (20080025122)
Abstract
A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.
Memory Systems and Memory Modules (20080010435)
Abstract
One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.
Method and Apparatus for Refresh Management of Memory Modules (20080028136) Method and apparatus for refresh management of memory modules (20080109598) Method and Apparatus For Refresh Management of Memory Modules (20080028137) Method and Apparatus For Refresh Management of Memory Modules (20080109597)
Abstract
One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
Methods and apparatus of stacking DRAMs (20070058471)
Abstract
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies (20070014168)
Abstract
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.
Multiple-Component Memory Interface System and Method (20080028135)
Abstract
A system and method are provided, wherein a first component and a second component are operable to interface a plurality of memory circuits and a system.
System and Method for Adjusting the Timing of Signals Associated with a Memory System (20080115006)
Abstract
A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits (20080025108)
Abstract
A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component can receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage (20080086588)
Abstract
In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system. The interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.
System and Method for Reducing Command Scheduling Constraints of Memory Circuits (20080109595) System and Method for Reducing Command Scheduling Constraints of Memory Circuits (20070204075) System and Method for Reducing Command Scheduling Constraints of Memory Circuits (20080120443)
Abstract
A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
System and Method for Simulating a Different Number of Memory Circuits (20080027702)
Abstract
A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.
System and Method for Simulating an Aspect of a Memory Circuit (20090285031)
Abstract
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Under various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
System and Method for Simulating an Aspect of a Memory Circuit (20080062773) System and Method for Simulating an Aspect of a Memory Circuit (20080133825)
Abstract
A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
Abstract
A system and method are provided for use in the context of a plurality of memory circuits. First information is received in association with a first operation to be performed on at least one of the memory circuits. At least a portion of the first information is stored. Still yet, second information is received in association with a second operation to be performed on at least one of the plurality of memory circuits. To this end, the second operation may be performed utilizing the stored portion of the first information and the second information.
System and Method for Translating an Address Associated with a Command Communicated between a System and Memory Circuits (20070192563)
Abstract
A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.