It’s a tangled web when it comes to patent acqusitions and infringement lawsuits, and a scorecard isn’t enough to keep track of the all of the businesses involved and the nature of their relationships with one another, as a recent acquisition of patents by Google from Mosaid Technologies illustrates.
In mid-September it was reported that Mosaid Technologies sold $11 million worth of patents to an undisclosed technology company. The purchased involved 5 patent families that Mosaid considered non-strategic patents because there were no licensing deals in place on the patents. It was supposedly the largest sale of intellectual property by the company since they started licensing technology patents around 4 years ago.
According to the US Patent and Trademark database, Google was recently assigned a number of patents from Mosaid Technologies. The assignment was executed on September 9th, and recorded on September 20th. The patents acquired by Google sound similar to those described in the news report I linked to above, involving technologies covering flash memory, encoding data, data compression, database search, and encryption approaches. Originally, a number of these patents appear to have originated at companies other than Mosaid Technologies, including Micron Quantum Devices, Inc., Purple Ray, Inc., Integrated Silicon Solution, Inc., and Chrysalis-ITS, Inc. (which was acquired by Safenet).
If you’ve heard about Mosaid Technologies recently, it may have been because they’ve been involved in some newsworthy events. For example, they acquired Core Wireless Licensing S.a.r.l. at the start of September, which holds approximately 2,000 patents originally filed by Nokia:
The patents and patent applications cover technologies used in a wide range of mobile communications devices and services. One hundred of the patent families, consisting of approximately 1,200 patents and applications, have been declared essential to second, third and fourth-generation communications standards, including GSM (Global Systems for Mobile communications), UMTS / WCDMA (Universal Mobile Telecommunications Service / Wide-Band Code Division Multiple Access) and LTE (Long Term Evolution). The rest of the portfolio consists of approximately 800 wireless implementation patents.
Microsoft and Nokia appear to be parties to that deal, and will collect approximately 2/3rds of the income generated from the licensing of the technology. The acquisition comes at a time when Mosaid is fighting off a hostile takeover by local rival Wilan, which is another Canadian company that holds a large number of mobile technology patents.
Mosaid also initiated at least a couple of high profile legal battles this year, with a suit filed in March against Dell and a number of other defendants, and another started in June (pdf) against Sonny Ericsson Mobile Communications (USA), Inc. and HTC America, Inc.
Mosiad was founded in 1975, and developed a wide range of semiconductor IP including “key circuit technology that is used in virtually all mainstream Dynamic Random Access Memory (DRAM) products – the main type of memory used in computers.”
The patents from the assignment filed at the USPTO are listed below, and do not include any possible unpublished patents, or any patents that might be listed in patent offices outside of the United States. There do appear to be 5 “families” of patents included in the transaction as described in the Mosaid Press release, and I’ve separated each family by lines of asterisks.
In this first pair of patents, the second is a continuation of the first:
Segmented non-volatile memory array with multiple sources with improved word line control circuitry Invented by Christophe J. Chevallier and Vinod C. Lakhani Assigned to Micron Quantum Devices, Inc. US Patent 5,673,224 Granted September 30, 1997 Filed: February 23, 1996
Segmented non-volatile memory array with multiple sources with improved word line control circuitry Invented by Christophe J. Chevallier and Vinod C. Lakhani Assigned to Micron Technology, Inc. US Patent 5,959,884 Granted September 28, 1999 Filed: September 12, 1997
Abstract
A flash memory array arrangement having a plurality of erase blocks which can be separately erased, preferably using negative gate erase techniques. The memory cells are arranged in each erase block to form an array of cell rows and cell columns, with the sources of the cells in each erase block connected to a common source line so as to permit separate erasure. Cells located in row have their control gates connected to a common word line and cells located in one of the columns having their drains connected to a common bit line.
The cells located in each erase block have their sources connected to a common source line. Word line control circuitry functions to control the state of the word lines in read, program and erase operations. Separate erase transistors are connected to each word line for the purpose of connecting the word lines of a block to be erased to a negative voltage. The erase transistors associated with blocks other than the block being erased cause the associated word lines to be in a state so that erasure will not occur in those deselected blocks.
In this pair, the second patent listed is a continuation of the first:
System and method for encoding data to reduce power and time required to write the encoded data to a flash memory Invented by Robert D. Norman Assigned to Micron Technology, Inc. US Patent 5,873,112 Granted February 16, 1999 Filed: October 15, 1996
System and method for encoding data to reduce power and time required to write the encoded data to a flash memory Invented by Robert D. Norman Assigned to Micron Technology, Inc. US Patent 6,292,868 Granted September 18, 2001 Filed: September 3, 1998
Abstract
A method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. Preferably, a count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal.
In some embodiments, each erased cell is indicative of the binary value “1”, the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. In alternative embodiments, a count signal is generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Preferably, flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.
The following patents share common inventors and seem to have originated at Integrated Silicon Solution, Inc., making them a separate “family” of patents. Unlike most of the other patents in this acquisition, this group actually appears to be related to search, though it’s hard to tell whether or not the technologies involved might be something that Google could use for its search.
Large database search using content addressable memory and hash Invented by Paul Cheng, Nelson L. Chow, and Fangli Chien Assigned to Integrated Silicon Solution, Inc. US Patent 6,889,225 Granted May 3, 2005 Filed: August 9, 2001
Abstract
A hash-CAM (H-CAM) which may work with a controller and a memory containing a database of either search values and associate content or associate content by itself The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the respectively paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to a single address value usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle newly determined hash collisions.
Search engine for large database search using hash pointers Invented by Paul Cheng, Nelson L. Chow, and Fangli Chien Assigned to Integrated Silicon Solution, Inc. US Patent 6,917,934 Granted July 12, 2005 Filed: September 30, 2002
Abstract
A search engine (100) having a controller (112), a memory (114), and a hash pointer unit (110). The memory (114) includes a database of search data and associate content, and the controller (112) uses individual search values to access the memory (114) to obtain individual search results. The controller (112) includes a hash function (116) that generates a hash value from a, typically large, search value into a, typically smaller, hash value that may be a hash collision. The controller (112) converts the hash value into a hash address which is communicated to the hash pointer unit (110), which receives the hash address and provides a hash pointer that is communicated to and used by the memory to look up respective search results. In this manner hash collisions are avoided and the size of the memory (114) is not a function of the degree of multi-way set-associativity used.
Search engine for large database search using CAM and hash Invented by Paul Cheng, Nelson L. Chow, and Fangli Chien Assigned to Integrated Silicon Solution, Inc. US Patent 7,107,258 Granted September 12, 2006 Filed: September 30, 2002
Abstract
A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to address values usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle new search data based hash collisions. The H-CAM may optionally also be cascaded.
The following 5 patents include continuations as well, and share a common Abstract:
Method and apparatus for adaptive data compression Invented by Mourad Abdat Assigned to Mosaid Technologies, Inc. US Patent 6,606,040 Granted August 12, 2003 Filed: February 13, 2001
Method and apparatus for adaptive data compression Invented by Mourad Abdat Assigned to Mosaid Technologies, Inc. US Patent 6,700,512 Granted March 2, 2004 Filed: April 18, 2003
Method and apparatus for adaptive data compression Invented by Mourad Abdat Assigned to MOSAID Technologies, Inc. US Patent 6,879,271 Granted April 12, 2005 Filed: February 27, 2004
Method and apparatus for adaptive data compression Invented by Mourad Abdat Assigned to MOSAID Technologies, Inc. US Patent Application 20060071822 Published April 6, 2006 Filed: March 9, 2005
Method and apparatus for adaptive data compression Invented by Mourad Abdat US Patent Application 20070030179 Published February 8, 2007 Filed: July 19, 2006
Abstract
We present a method and apparatus for performing adaptive data compression. An alphabet and vocabulary in the encoder and decoder is built adaptively and stored in a dictionary as symbols are to be encoded and decoded. Each time an unknown symbol is to be encoded by the encoder, the encoder adds the symbol to the dictionary and transmits it in plain in the encoded string. The code words transmitted by the encoder include symbols and indexes. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary.
The decoder examines the prefix bit of each code word as it is received to determine if the code word stores a symbol in plain or in index. If the code word stores a symbol in plain, the decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary. If the code word stores an index, the decoder decodes the code word by extracting the symbol or sequence of symbols stored in the dictionary at the respective index in the dictionary.
The second and third patents listed in the three below are continuations, and they share a common abstract:
Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies Invented by Hafid Zaabab Assigned to MOSAID Technologies Incorporated US Patent 7,451,326 Granted November 11, 2008 Filed: August 26, 2002
Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies Invented by Hafid Zaabab Assigned to MOSAID Technologies Incorporated US Patent 7,962,758 Granted June 14, 2011 Filed: October 14, 2008
Method And Apparatus For Processing Arbitrary Key Bit Length Encryption Operations With Similar Efficiencies Invented by Hafid Zaabab Assigned to MOSAID Technologies Incorporated US Patent Application 20110208976 Published August 25, 2011 Filed: April 28, 2011
Abstract
A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.
The second and third patents listed in the three below are continuations, and they share a common abstract:
Dense mode coding scheme Invented by David A. Brown and Peter B. Gillingham Assigned to MOSAID Technologies Incorporated US Patent 7,346,009 Granted March 18, 2008 Filed: September 30, 2002
Dense mode coding scheme Invented by David A. Brown and Peter B. Gillingham Assigned to MOSAID Technologies Incorporated US Patent 7,633,960 Granted December 15, 2009 Filed: January 4, 2008
Dense mode coding scheme Invented by David A. Brown and Peter B. Gillingham Assigned to MOSAID Technologies Incorporated US Patent 8,023,519 Granted September 20, 2011 Filed: November 4, 2009
Abstract
A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.
Conclusion
My primary interest in following Google’s transactions are what it might mean to search and Google’s search engine. Google is continuing to acquire a wide range of technology patents with this acquisition, many of which don’t necessarily appear to focus upon search.
The timing of this acquistion, and the company that Google purchased the intellectual property from is interesting given Mosaid’s acquisition of the Nokia patents from Core Wireless, which appears to have been created a number of months ago, possibly for purposes of making it easy to make the transition of the patents to Mosaid (or another company) possible. Josh Kosman, in a New York Post article on September 15th, Patently False says about the transaction:
But the strangely structured deal has raised eyebrows among competitors, in particular Google. Sources said Google is concerned that Mosaid will launch a flurry of patent infringement suits against smartphone makers using Google’s Android software.
Google appears to have been the “undisclosed” tech company that provided Mosaid with their largest influx of cash involving a patent transaction in more than 4 years.
Wondering what the relationship is like between Google and Mosaid these days…
Added 2011-9-28 @ 4:55 et – A spokesperson from Mosaid Technologies confirmed this afternoon to the Wall Street Journal and Reuters that Google was the subject of the press release it issued 2 weeks ago. (Not sure that an official confirmation was necessary, since the USPTO assignment database is a matter of public record, but it’s nice to see…)
Added 2011-9-28 @ 7:58 et – Dylan McGrath of the EE Times has also reported on this story, and is the first media site to point to this post as where Google was first identified publicly as the purchaser of those patents.